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| PRELIMINARY TECHNICAL DATA a 8/10/12/14-Bit High Bandwidth Multiplying DACs with Serial Interface Preliminary Technical Data AD5450/AD5451/AD5452/AD5453* FUNCTIONAL BLOCK DIAGRAM VDD FEATURES +2.5 V to +5.5 V Supply Operation 50MHz Serial Interface 10MHz Multiplying Bandwidth 10V Reference Input 8-Lead TSOT & MSOP Packages Pin Compatible 8, 10, 12 and 14 Bit Current Output DACs Extended Temperature range -40C to +125C Guaranteed Monotonic Four Quadrant Multiplication Power On Reset with brown out detect <5A typical Current Consumption APPLICATIONS Portable Battery Powered Applications Waveform Generators Analog Processing Instrumentation Applications Programmable Amplifiers and Attenuators Digitally-Controlled Calibration Programmable Filters and Oscillators Composite Video Ultrasound Gain, offset and Voltage Trimming SYNC SCLK SDIN VREF R 8/10/12/14 BIT R-2R DAC RFB IOUT1 AD5450/ AD5451/ AD5452/ AD5453 DAC REGISTER Power On Reset INPUT LATCH CONTROL LOGIC & INPUT SHIFT REGISTER GND GENERAL DESCRIPTION The AD5450/AD5451/AD5452/AD5453 are CMOS 8, 10, 12 and 14-bit Current Output digital-to-analog converters respectively. These devices operate from a +2.5 V to 5.5 V power supply, making them suited to battery powered applications and many other applications. These DACs utilize double buffered 3-wire serial interface that is compatible with SPITM, QSPITM, MICROWIRETM and most DSP interface standards. On power-up, the internal shift register and latches are filled with zeros and the DAC output is at zero scale. As a result of manufacture on a CMOS sub micron process, they offer excellent four quadrant multiplication characteristics, with large signal multiplying bandwidths of 10MHz. The applied external reference input voltage (VREF) determines the full scale output current. An integrated feedback resistor (RFB) provides temperature tracking and full scale voltage output when combined with an external Current to Voltage precision amplifier. The AD5450/AD5451/AD5452/AD5453 DACs are available in small 8-lead TSOT & MSOP packages. *US Patent Number 5,689,257 SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation. REV. PrD Oct, 2003 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P Box 9106, Norwood, MA 02062-9106, U.S.A. .O. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2003 PRELIMINARY TECHNICAL DATA AD5450/AD5451/AD5452/AD5453-SPECIFICATIONS1 measured with (V = 2.5 V to 5.5 V, V = +10 V, I x = O V. All specifications T to T unless otherwise noted. DC performance DD REF OUT MIN MAX OP1177, AC performance with AD9631 unless otherwise noted.) Parameter STATIC PERFORMANCE AD5450 Resolution Relative Accuracy Differential Nonlinearity AD5451 Resolution Relative Accuracy Differential Nonlinearity AD5452 Resolution Relative Accuracy Differential Nonlinearity AD5453 Resolution Relative Accuracy Differential Nonlinearity Total Unadjusted Error Gain Error Gain Error Temp Coefficient 2 Output Leakage Current Output Voltage Compliance Range REFERENCE INPUT Reference Input Range V REF Input Resistance DIGITAL INPUTS Input High Voltage, V IH Input Low Voltage, V IL Input Leakage Current, I IL Input Capacitance DYNAMIC PERFORMANCE 2 2 2 Min Typ Max Units Conditions 8 0.25 1/2 10 0.25 1/2 12 0.5 1/2 14 2 1 2.44 1.22 5 10 50 1.23 10 9.3 Bits LSB LSB Bits LSB LSB Bits LSB LSB Guaranteed Monotonic Guaranteed Monotonic Guaranteed Monotonic Bits LSB LSB Guaranteed Monotonic mV mV ppm FSR/C nA Data = 0000H, TA = 25C, IOUT1 nA Data = 0000H, IOUT1 V V k V V V V A pF 8 2.0 1.7 12 Input resistance TC = -50ppm/C VDD VDD VDD VDD = = = = 3.6 2.5 2.7 2.5 V V V V to to to to 5V 3.6 V 5.5 V 2.7 V 0.8 0.7 1 10 Reference Multiplying BW Output Voltage Settling Time AD5450 AD5451 AD5452 AD5453 Digital Delay 10% to 90% Dettling Time Digital to Analog Glitch Impulse Multiplying Feedthrough Error 10 MHz 100 110 160 180 20 10 3 -75 40 30 ns ns ns ns ns ns nV-s dB VREF = +/-3.5V, DAC loaded all 1s VREF = 10V, RLOAD = 100, CLOAD = 15pF DAC latch alternately loaded with 0s and 1s. Measured to +/-16mV of FS Measured to +/-4mV of FS Measured to +/-1mV of FS Measured to +/-1mV of FS Interface delay time Rise and Fall time, VREF = 10V, RLOAD = 100, CLOAD = 15pF 1 LSB change around Major Carry, V REF=0V DAC latch loaded with all 0s. Reference = 1MHz. Reference = 10MHz. DAC Latches Loaded with all 0s DAC Latches Loaded with all 1s DAC Latches Loaded with all 0s DAC Latches Loaded with all 1s Feedthrough to DAC output with CS high and Alternate Loading of all 0s and all 1s. Output Capacitance IOUT1 IOUT2 Digital Feedthrough 5 10 10 5 0.1 pF pF pF pF nV-s -2- REV. PrD PRELIMINARY TECHNICAL DATA AD5450/AD5451/AD5452/AD5453 (VDD = 2.5 V to 5.5 V, VREF = +10 V, IOUTx = O V. All specifications TMIN to TMAX unless otherwise noted. DC performance measured with OP1177, AC performance with AD9631 unless otherwise noted.) Parameter Total Harmonic Distortion Digital THD, Clock = 1MHz 50kHz fOUT Output Noise Spectral Density SFDR performance (Wideband) Update = 1MHz 50kHz Fout 20kHz Fout SFDR performance (NarrowBand) 50kHz Fout 20kHz Fout Intermodulation Distortion POWER REQUIREMENTS Power Supply Range IDD Power Supply Sensitivity 2 Min Typ -80 75 25 Max Units dB dB nV/Hz Conditions VREF = 3.5 V pk-pk, All 1s loaded, f = 1kHz @ 1kHz Update = 1MHz, V REF = 3.5V 78 78 87 87 78 dB dB Update = 1MHz, V REF = 3.5V dB dB dB f1 = 20kHz, f2 = 25kHz, Update=1MHz, V REF =3.5V 2.5 5.5 1 0.001 V A %/% Logic Inputs = 0 V or VDD = 5% VDD NOTES 1 Temperature range is as follows: Y Version: -40C to +125C. 2 Guaranteed by design and characterisation, not subject to production test. Specifications subject to change without notice. TIMING CHARACTERISTICS1(V Parameter f SCLK t1 t2 t3 t4 t5 t6 t7 t8 VDD = 4.5 V to 5.5 V 50 20 8 8 8 5 4.5 5 30 REF = +5 V, IOUT2 = O V. All specifications TMIN to TMAX unless otherwise noted.) Conditions/Comments Max Clock frequency SCLK Cycle time SCLK High Time SCLK Low Time SYNC falling edge to SCLK active edge setup time Data Setup Time Data Hold Time SYNC rising edge to SCLK active edge Minimum SYNC high time MHz max ns min ns min ns min ns min ns min ns min ns min ns min VDD = 2.5 V to 5.5 V Units NOTES 1 See Figures 1. Temperature range is as follows: Y Version: -40C to +125C. Guaranteed by design and characterisation, not subject to production test. All input signals are specified with tr =tf = 5ns (10% to 90% of VDD ) and timed from a voltage level of (V IL + V IH)/2. Specifications subject to change without notice. t1 SCLK t2 t8 t4 SYNC t6 t5 DIN DB15 DB0 t3 t7 Figure 1. Timing Diagram. REV. PrD -3- PRELIMINARY TECHNICAL DATA AD5450/AD5451/AD5452/AD5453 ABSOLUTE MAXIMUM RATINGS1, (TA = +25C unless otherwise noted) 2 VDD to GND -0.3 V to +7 V VREF, RFB to GND -12 V to +12 V IOUT1 to GND -0.3 V to +7 V 10 mA Input Current to any pin except supplies Logic Inputs & Output3 -0.3V to VDD +0.3 V Operating Temperature Range Industrial (Y Version) -40C to +125C Storage Temperature Range -65C to +150C Junction Temperature +150C 206C/W 8 lead MSOP JA Thermal Impedance 8 lead TSOT JA Thermal Impedance 211C/W Lead Temperature, Soldering (10seconds) 300C IR Reflow, Peak Temperature (<20 seconds) +235C NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Transient currents of up to 100mA will not cause SCR latchup. 3 Overvoltages at SCLK, SYNC, DIN, will be clamped by internal diodes. Current should be limited to the maximum ratings given. ORDERING GUIDE Model AD5450YUJ AD5451YUJ AD5452YUJ AD5452YRM AD5453YUJ AD5453YRM Resolution 8 10 12 12 14 14 INL 0.25 0.25 0.5 0.5 2 2 Temperature Range -40 -40 -40 -40 -40 -40 o o Package Description Branding TSOT TSOT TSOT MSOP TSOT MSOP Package Option UJ-8 UJ-8 UJ-8 RM-8 UJ-8 RM-8 C C o C o C o C o C to to to to to to +125 +125 +125 +125 +125 +125 o o C C o C o C o C o C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5450/AD5451/AD5452/AD5453 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. -4- REV. PrD PRELIMINARY TECHNICAL DATA AD5450/AD5451/AD5452/AD5453 PIN FUNCTION DESCRIPTION MSOP 1 2 3 TSOT 8 7 6 Mnemonic Function I OUT 1 GND SCLK DAC Current Output. Ground Pin. Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock input. Alternatively, by means of the serial control bits, the device may be configured such that data is clocked into the shift register on the rising edge of SCLK. Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By default, on power up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the user to change the active edge to rising edge. Active Low Control Input. This is the frame synchronization signal for the input data. Data is loaded to the shift register on the active edge of the following clocks. Positive power supply input. These parts can operate from a supply of +2.5 V to +5.5 V. DAC reference voltage input pin. DAC feedback resistor pin. Establish voltage output for the DAC by connecting to external amplifier output. 4 5 SDIN 5 4 SYNC 6 7 8 3 2 1 V DD V REF RFB PIN CONFIGURATION TSOT (UJ-8) AD5450/ AD5451/ VREF 2 AD5452/ AD5453 VDD 3 (Not to Scale) SYNC 4 RFB 1 8 IOUT1 7 GND 6 SCLK 5 SDIN MSOP (RM-8) IOUT1 1 AD5452/ AD5453 SCLK 3 (Not to Scale) GND 2 SDIN 4 8 RFB 7 VREF 6 VDD 5 SYNC REV. PrD -5- PRELIMINARY TECHNICAL DATA AD5450/AD5451/AD5452/AD5453 TERMINOLOGY Relative Accuracy Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero and full scale and is normally expressed in LSBs or as a percentage of full scale reading. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of -1 LSB max over the operating temperature range ensures monotonicity. Gain Error Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For these DACs, ideal maximum output is VREF - 1 LSB. Gain error of the DACs is adjustable to zero with external resistance. Output Leakage Current Output leakage current is current which flows in the DAC ladder switches when these are turned off. For the IOUT1 terminal, it can be measured by loading all 0s to the DAC and measuring the IOUT1 current. Minimum current will flow in the IOUT2 line when the DAC is loaded with all 1s Output Capacitance Capacitance from IOUT1 or IOUT2 to AGND. Output Current Settling Time This is the amount of time it takes for the output to settle to a specified level for a full scale input change. For these devices, it is specifed with a 100 resistor to ground. The settling time specification includes the digital delay from SYNC rising edge to the full scale output change. Digital to Analog Glitch lmpulse The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-secs or nV-secs depending upon whether the glitch is measured as a current or voltage signal. Digital Feedthrough When the device is not selected, high frequency logic activity on the device digital inputs may be capacitivelly coupled through the device to show up as noise on the IOUT pins and subsequently into the following circuitry. This noise is digital feedthrough. Multiplying Feedthrough Error This is the error due to capacitive feedthrough from the DAC reference input to the DAC IOUT1 terminal, when all 0s are loaded to the DAC. Total Harmonic Distortion (THD) The DAC is driven by an ac reference. The ratio of the rms sum of the harmonics of the DAC output to the fundamental value is the THD. Usually only the lower order harmonices are included, such as second to fifth. THD = 20log (V22 + V32 + V42 + V52) V1 Digital Intermodulation Distortion Second order intermodulation (IMD) measurements are the relative magnitudes of the fa and fb tones generated digitally by the DAC and the second order products at 2fa-fb and 2fb-fa. Compliance Voltage Range The maximum range of (output) terminal voltage for which the device will provide the specified characteristics. Spurious-Free Dynamic Range(SFDR) It is the usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. SFDR is the measure of difference in amplitude between the fundamental and the largest harmonically or nonharmonically related spur from dc to full Nyquist bandwidth (half the DAC sampling rate or fs/2). Narrow band SFDR is a measure of SFDR over an arbitrary window size, in this case 50% of hte fundamental. Digital SFDR is a measure of the usable dymanic range of the DAC when the signal is a digitally generated sine wave. -6- REV. PrD PRELIMINARY TECHNICAL DATA Typical Performance Characteristics AD5450/AD5451/AD5452/AD5453 TPC 1. INL vs. Code (8-Bit DAC) TPC 2. INL vs. Code (10-Bit DAC) TPC 3. INL vs. Code (12-Bit DAC) TPC 4. INL vs. Code (14-Bit DAC) TPC 5. DNL vs. Code (8-Bit DAC) TPC 6. DNL vs. Code (10-Bit DAC) TPC 7. DNL vs. Code (12-Bit DAC) TPC 8. DNL vs. Code (14-Bit DAC) TPC 9. INL vs Reference Voltage REV. PrD -7- PRELIMINARY TECHNICAL DATA AD5450/AD5451/AD5452/AD5453 TPC10. DNL vs. Reference Voltage TPC11. Linearity Errors vs. VDD TPC12. INL vs Code - Biased Mode TPC 13. DNL vs Code - Biased Mode TPC 14. INL Error vs. Reference Biased Mode TPC 15. DNL Error vs. Reference Biased Mode TPC 16. TUE vs Code TPC 17. Supply Current vs. Clock Freq TPC 18. Logic Threshold vs Supply Voltage -8- REV. PrD PRELIMINARY TECHNICAL DATA AD5450/AD5451/AD5452/AD5453 TPC 19. Supply Current vs Logic Input Voltage TPC 20. Reference Multiplying Bandwidth - small signal TPC 21. Reference Multiplying Bandwidth - large signal TPC 22. Reference Multiplying Bandwidth - small signal TPC 23. Reference Multiplying Bandwidth - large signal TPC 24. Settling Time TPC 25. Midscale Transition and Digital Feedthrough TPC 26. Power Supply Rejection vs Frequency TPC 27. Noise Spectral Density vs Frequency REV. PrD -9- PRELIMINARY TECHNICAL DATA AD5450/AD5451/AD5452/AD5453 TPC 28. TBD TPC 29. TBD TPC 30. TBD -10- REV. PrD PRELIMINARY TECHNICAL DATA AD5450/AD5451/AD5452/AD5453 GENERAL DESCRIPTION DAC SECTION The AD5450, AD5451, AD5452 and AD5453 are 8, 10, 12 and 14 bit current output DACs consisting of a segmented (4-Bits) inverting R-2R ladder configuration. The feedback resistor RFB has a value of R. The value of R is typically 9.3k (minimum 8k and maximum 12k). If IOUT1 is kept at the same potential as GND, a constant current flows in each ladder leg, regardless of digital input code. Therefore, the input resistance presented at VREF is always constant and nominally of value R. The DAC output (IOUT) is code-dependent, producing various resistances and capacitances. External amplifier choice should take into account the variation in impedance generated by the DAC on the amplifiers inverting input node. Access is provided to the VREF, RFB, and IOUT1 terminals of the DAC, making the device extremely versatile and allowing it to be configured in several different operating modes, for example, to provide a unipolar output and in four quadrant multiplication in bipolar mode. Note that a matching switch is used in series with the internal RFB feedback resistor. If users attempt to measure RFB, power must be applied to VDD to achieve continuity. SERIAL INTERFACE similarly the AD5451 uses ten bits and ignores the four LSBs, while the AD5450 uses eight bits and ignores the last six bits. DAC Control Bits C1, C0 Control bits C1 and C0 the user to load and update the new DAC code and to change the active clock edge. By default the shift register clocks data in on the falling edge, this can be changed via the control bits. In this case, the DAC core is inoperative until the next data frame. A power cycle resets this back to default condition. On chip power on reset circuitry ensures the device powers on with zeroscale loaded to the DAC register and IOUT line. TABLE III. DAC CONTROL BITS C1 0 0 1 1 C0 Funtion Implemented 0 1 0 1 Load and Update(Power On Default) Reserved Reserved Clock Data to shift register On Rising Edge SYNC Function The AD5450/AD5451/AD5452/AD5453 have an easy to use 3-wire interface which is compatible with SPI/QSPI/ MicroWire and DSP interface standards. Data is written to the device in 16 bit words. This 16-bit word consists of 2 control bits and either 8, 10 12, or 14 data bits as shown in Figure 2. The AD5453 uses all 14 bits of DAC data. The AD5452 uses twelve bits and ignores the two LSBs, DB15 (MSB) C1 C0 DB7 DB6 DB5 DB4 SYNC is an edge-triggered input that acts as a frame synchronization signal and chip enable. Data can only be transferred into the device while SYNC is low. To start the serial data transfer, SYNC should be taken low observing the minimum SYNC falling to SCLK falling edge setup time, t4. After the falling edge of the 16th SCLK pulse, bring SYNC high to transfer data from the input shift register to the DAC register. DB0 (LSB) DB3 DB2 DB1 DB0 DATA BITS X X X X X X CONTROL BITS Figure 2a. AD5450 8 bit Input Shift Register Contents DB15 (MSB) C1 C0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X DB0 (LSB) X X DATA BITS CONTROL BITS Figure 2b. AD5451 10 bit Input Shift Register Contents DB15 (MSB) C1 C0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DATA BITS CONTROL BITS DB3 DB2 DB1 DB0 DB0 (LSB) X X Figure 2c. AD5452 12 bit Input Shift Register Contents DB15 (MSB) C1 C0 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DATA BITS CONTROL BITS DB5 DB4 DB3 DB2 DB0 (LSB) DB1 DB0 Figure 2c. AD5453 14 bit Input Shift Register Contents REV. PrD -11- PRELIMINARY TECHNICAL DATA AD5450/AD5451/AD5452/AD5453 CIRCUIT OPERATION Unipolar Mode Using a single op amp, these devices can easily be configured to provide 2 quadrant multiplying operation or a unipolar output voltage swing as shown in Figure 3. When an output amplifier is connected in unipolar mode, the output voltage is given by: VOUT = -D/2n x VREF Where D is the fractional representation of the digital word loaded to the DAC, and n is the number of bits. D= = = = 0 0 0 0 to to to to 255 (8-Bit AD5450) 1023 (10-Bit AD5451) 4095 (12-Bit AD5452) 16383 (14-Bit AD5453) With a fixed 10 V reference, the circuit shown above will give an unipolar 0V to -10V output voltage swing. When VIN is an ac signal, the circuit performs two-quadrant multiplication. The following table shows the relationship between digital code and expected output voltage for unipolar operation. (AD5450, 8-Bit device). Table I. Unipolar Code Table Digital Input 1111 1000 0000 0000 1111 0000 0001 0000 Analog Output (V) -V REF (255/256) -VREF (128/256) = -VREF/2 -V REF (1/256) -VREF (0/256) = 0 Note that the output voltage polarity is opposite to the VREF polarity for dc reference voltages. VDD R2 Bipolar Operation C1 VDD VREF R1 VREF AD5450/1/2/3 GND SYNC SCLK SDIN AGND uController NOTES: 1R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 2C1 PHASE COMPENSATION (1pF - 5pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. VOUT = 0 to -VREF RFB IOUT1 A1 In some applications, it may be necessary to generate full 4-Quadrant multplying operation or a bipolar output swing. This can be easily accomplished by using another external amplifier and some external resistors as shown in Figure 4. In this circuit, the second amplifier A2 provides a gain of 2. Biasing the external amplifier with an offset from the reference voltage results in full 4-quadrant multiplying operation. The transfer function of this circuit shows that both negative and positive output voltages are created as the input data (D) is incremented from code zero (VOUT = - VREF) to midscale (VOUT - 0V ) to full scale (VOUT = + VREF). VOUT = (VREF x D / 2n-1 ) - VREF Where D is the fractional representation of the digital word loaded to the DAC and n is the resolution of the DAC. D= = = = 0 0 0 0 to to to to 255 (8-Bit AD5450) 1023 (10-Bit AD5451) 4095 (12-Bit AD5452) 16383 (14-Bit AD5453) Figure 3. Unipolar Operation These DACs are designed to operate with either negative or positive reference voltages. The VDD power pin is only used by the internal digital logic to drive the DAC switches' ON and OFF states. These DACs are also designed to accommodate ac reference input signals in the range of -10V to +10V. When VIN is an ac signal, the circuit performs fourquadrant multiplication. Table II. shows the relationship between digital code and the expected output voltage for bipolar operation (AD5450, 8-Bit device). R3 20k VDD VDD VREF AD5450/1/2/3 SYNC SCLK SDIN RFB IOUT1 GND R2 C1 A1 R4 10k A2 VOUT = -VREF to +VREF R5 20k R1 VREF 10V uController AGND NOTES: 1R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADED TO DAC. 2MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4. 3C1 PHASE COMPENSATION (1pF-5pF) MAY BE REQUIRED IF A1/A2 IS A HIGH SPEED AMPLIFIER. Figure 4. Bipolar Operation (4 Quadrant Multiplication) -12- REV. PrD PRELIMINARY TECHNICAL DATA AD5450/AD5451/AD5452/AD5453 Table II. Bipolar Code Table ratings of the device. In this type of application, the full range of multiplying capability of the DAC is lost. POSITIVE OUTPUT VOLTAGE Digital Input 1111 1000 0000 0000 1111 0000 0001 0000 Analog Output (V) +V REF (127/128) 0 -V REF (127/128) -V REF (128/128) Stability In the I-to-V configuration, the IOUT of the DAC and the inverting node of the op amp must be connected as close as possible, and proper PCB layout techniques must be employed. Since every code change corresponds to a step function, gain peaking may occur if the op amp has limited GBP and there is excessive parasitic capacitance at the inverting node. This parasitic capacitance introduces a pole into the open loop response which can cause ringing or instability in the closed loop applications circuit. An optional compensation capacitor, C1 can be added in parallel with RFB for stability as shown in figures 3 and 4. Too small a value of C1 can produce ringing at the output, while too large a value can adversely affect the settling time. C1 should be found empirically but 1-2pF is generally adequate for the compensation. SINGLE SUPPLY APPLICATIONS Voltage Switching Mode of Operation Note that the output voltage polarity is opposite to the VREF polarity for dc reference voltages. In order to achieve a positive voltage output, an applied negative reference to the input of the DAC is preferred over the output inversion through an inverting amplifier because of the resistors tolerance errors. To generate a negative reference, the reference can be level shifted by an op amp such that the VOUT and GND pins of the reference become the virtual ground and -2.5V respectively as shown in Figure 6. VDD = 5V ADR03 VOUT VIN GND + 5V VDD -2.5V 1/2 AD8552 GND - 5V VREF RFB IOUT1 IOUT2 1/2 AD8552 VOUT = 0 to +2.5V C1 Figure 5 shows these DACs operating in the voltageswitching mode. The reference voltage, VIN is applied to the IOUT1 pin, IOUT2 is connected to AGND and the output voltage is available at the VREF terminal. In this configuration, a positive reference voltage results in a positive output voltage making single supply operation possible. The output from the DAC is voltage at a constant impedance (the DAC ladder resistance). Thus an op-amp is necessary to buffer the output voltage. The reference input no longer sees a constant input impedance, but one that varies with code. So, the voltage input should be driven from a low impedance source. VDD NOTES: 1ADDITIONAL PINS OMITTED FOR CLARITY 2C1 PHASE COMPENSATION (1pF-5pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. Figure 6. Positive Voltage output with minimum of components. ADDING GAIN R1 R2 RFB VIN VDD VREF GND VOUT IOUT1 In applications where the output voltage is required to be greater than VIN, gain can be added with an additional external amplifier or it can also be achieved in a single stage. It is important to take into consideration the effect of temperature coefficients of the thin film resistors of the DAC. Simply placing a resistor in series with the RFB resistor will causing mis-matches in the Temperature coefficients resulting in larger gain temperature coefficient errors. Instead, the circuit of Figure 7 is a recommended method of increasing the gain of the circuit. R1, R2 and R3 should all have similar temperature coefficients, but they need not match the temperature coefficients of the DAC. This approach is recommended in circuits where gains of great than 1 are required. NOTES: 1ADDITIONAL PINS OMITTED FOR CLARITY 2C1 PHASE COMPENSATION (1pF-5pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. Figure 5. Single Supply Voltage Switching Mode Operation. It is important to note that VIN is limited to low voltages because the switches in the DAC ladder no longer have the same source-drain drive voltage. As a result their on resistance differs and this degrades the integral linearity of the DAC. Also, VIN must not go negative by more than 0.3V or an internal diode will turn on, exceeding the max REV. PrD -13- PRELIMINARY TECHNICAL DATA AD5450/AD5451/AD5452/AD5453 VDD op amp through the DAC. Since only a fraction D of the current into the VREF terminal is routed to the IOUT1 terminal, the output voltage has to change as follows: RFB IOUT1 IOUT2 R3 R2 GAIN = R2 + R3 R2 R1 = R2R3 R2 + R3 C1 Output Error Voltage Due to Dac Leakage = (Leakage x R)/D VOUT VDD VIN R2 VREF GND where R is the DAC resistance at the VREF terminal. For a DAC leakage current of 10nA, R = 10 kilohm and a gain (i.e., 1/D) of 16 the error voltage is 1.6mV. REFERENCE SELECTION NOTES: 1ADDITIONAL PINS OMITTED FOR CLARITY 2C1 PHASE COMPENSATION (1pF-5pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. Figure 7. Increasing Gain of Current Output DAC USED AS A DIVIDER OR PROGRAMMABLE GAIN ELEMENT Current Steering DACs are very flexible and lend themselves to many different applications. If this type of DAC is connected as the feedback element of an op-amp and RFB is used as the input resistor as shown in Figure 8, then the output voltage is inversely proportional to the digital input fraction D. For D = 1-2n the output voltage is VOUT = -VIN /D = -VIN /(1-2-n) VDD VIN RFB IOUT1 GND VDD VREF When selecting a reference for use with the AD5426 series of current output DACs, pay attention to the references output voltage temperature coefficient specification. This parameter not only affects the full scale error, but can also affect the linearity (INL and DNL) performance. The reference temperature coefficient should be consistent with the system accuracy specifications. For example, an 8-bit system required to hold its overall specification to within 1LSB over the temperature range 0-50oC dictates that the maximum system drift with temperature should be less than 78ppm/oC. A 14-Bit system with the same temperature range to overall specification within 2LSBs requires a maximum drift of 10ppm/oC. By choosing a precision reference with low output temperature coefficient this error source can be minimized. Table IV. suggests some of the suitable dc references available from Analog Devices that are suitable for use with this range of current output DACs. AMPLIFIER SELECTION VOUT NOTES: 1ADDITIONAL PINS OMITTED FOR CLARITY Figure 8. Current Steering DAC used as a divider or Programmable Gain Element The primary requirement for the current-steering mode is an amplifier with low input bias currents and low input offset voltage. The input offset voltage of an op amp is multiplied by the variable gain (due to the code dependent output resistance of the DAC) of the circuit. A change in this noise gain between two adjacent digital fractions produces a step change in the output voltage due to the amplifier's input offset voltage. This output voltage change is superimposed upon the desired change in output between the two codes and gives rise to a differential linearity error, which if large enough could cause the DAC to be non-monotonic. The input bias curent of an op amp also generates an offset at the voltage output as a result of the bias current flowing in the feedback resistor RFB. Most op amps have input bias currents low enough to prevent any significant errors in 12-Bit applications, however for 14-Bit applications some consideration should be given to selecting an appropriate amplifier. Common mode rejection of the op amp is important in voltage switching circuits, since it produces a code dependent error at the voltage output of the circuit. Most op amps have adequate common mode rejection for use at 8-, 10- and 12-Bit resolution. Provided the DAC switches are driven from true wideband low impedance sources (VIN and AGND) they settle quickly. Consequently, the slew rate and settling time of a voltage switching DAC circuit is determined largely by the output op amp. To obtain minimum settling time in this configuration, it is important to minimize capacitance REV. PrD As D is reduced, the output voltage increases. For small values of the digital fraction D, it is important to ensure that the arnplifier does not saturate and also that the required accuracy is met. For example, an eight bit DAC driven with the binary code 10H (00010000), i.e., 16 decimal, in the circuit of Figure 8 should cause the output voltage to be sixteen times VIN. However, if the DAC has a linearity specification of +/- 0.5LSB then D can in fact have the weight anywhere in the range 15.5/256 to 16.5/256 so that the possible output voltage will be in the range 15.5VIN to 16.5VIN--an error of + 3% even though the DAC itself has a maximum error of 0.2%. DAC leakage current is also a potential error source in divider circuits. The leakage current must be counterbalanced by an opposite current supplied from the -14- PRELIMINARY TECHNICAL DATA AD5450/AD5451/AD5452/AD5453 Table IV. Listing of suitable ADI Precision References recommended for use with AD5450/1/2/3 DACs. Reference Output Voltage Initial Tolerance Temperature Drift 0.1Hz to 10Hz noise Package ADR01 ADR02 ADR03 ADR425 10 V 5V 2.5 V 5V 0.1% 0.1% 0.2% 0.04% 3ppm/ C 3ppm/ o C 3ppm/ o C 3ppm/ o C o 20Vp-p 10Vp-p 10Vp-p 3.4Vp-p SC70, TSOT, SOIC SC70, TSOT, SOIC SC70, TSOT, SOIC MSOP, SOIC Table V. Listing of some precision ADI Op Amps suitable for use with AD5450/1/2/3 DACs. Part # Max Supply Voltage V V OS (max) V IB(max) nA GBP MHz Slew Rate V/s t SETTLE with AD5453 OP97 20 OP1177 18 AD8551 6 25 60 5 0.1 2 0.05 0.9 1.3 1.5 0.2 0.7 0.4 Table VI. Listing of some High Speed ADI Op Amps suitable for use with AD5450/1/2/3 DACs. Part # Max Supply Voltage V BW @ ACL MHz Slew Rate V/s t SETTLE with AD5453 V OS (max) V I B(max) nA AD8065 AD8021 AD8038 AD9631 12 12 5 5 145 200 350 320 180 100 425 1300 1500 1000 3000 10000 0.01 1000 0.75 7000 at the VREF node (voltage output node in this application) of the DAC. This is done by using low inputs capacitance buffer amplifiers and careful board design. Most single supply circuits include ground as part of the analog signal range, which in turns requires an ampliferthat can handle rail to rail signals, there is a large range of single supply amplifiers available from Analog Devices. PCB LAYOUT AND POWER SUPPLY DECOUPLING Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a doublesided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. It is good practice to employ compact, minimum lead length PCB layout design. Leads to the input should be as short as possible to minimize IR drops and stray inductance. The PCB metal traces between VREF and RFB should also be matched to minimize gain error. To maximize on high frequency performance, the I-to-V amplifier should be located as close to the device as possible. In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5426/AD5432/AD5443 is mounted should be designed so that the analog and digital sections are separated, and cofined to certain areas of the board. If the DAC is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. These DACs should have ample supply bypassing of 10 F in parallel with 0.1 F on the supply located as close to the package as possible, ideally right up against the device. The 0.1 F capacitor should have low Effective Series Resistance (ESR) and Effective Series Inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. Low ESR 1 F to 10 F tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. REV. PrD -15- PRELIMINARY TECHNICAL DATA AD5450/AD5451/AD5452/AD5453 Overview of AD54xx devices Part # AD5403 1 Resolution #DACs 8 8 8 8 8 8 8 8 8 10 10 10 10 10 10 10 10 12 12 12 12 12 12 12 12 14 2 1 2 1 1 1 2 2 1 2 1 2 1 1 2 2 1 2 1 2 1 1 2 2 1 1 INL 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.25 1 1 1 1 1 1 1 0.5 2 tS 20ns 20ns 20ns 60ns 100ns 100ns 60ns 100ns 100ns 25ns 25ns 25ns Interface Parallel Serial Serial Parallel Serial Serial Parallel Serial Serial Parallel Serial Serial Package CP-40 Features AD5410 1 AD5413 1 AD5424 AD5425 AD5426 AD5428 2 AD5429 2 AD5450 2 AD5404 1 AD5411 1 AD5414 1 AD5432 AD5433 AD5439 2 AD5440 2 AD5451 2 AD5405 2 AD5412 1 AD5415 2 AD5443 AD5445 AD5447 2 AD5449 2 AD5452 2 AD5453 2 1 2 110ns Serial 70ns Parallel 110ns Serial 70ns Parallel 110ns Serial 120ns Parallel 160ns Serial 160ns Serial 160ns 120ns 120ns 160ns 160ns 180ns Serial Parallel Parallel Serial Serial Serial 10 MHz BW, 17 ns CS Pulse Width, 4Quadrant Multiplying Resistors RU-16 10 MHz BW, 50 MHz Serial, 4- Quadrant Multiplying Resistors RU-24 10 MHz BW, 50 MHz Serial, 4- Quadrant Multiplying Resistors RU-16, CP-20 10 MHz BW, 17 ns CS Pulse Width RM-10 Byte Load,10 MHz BW, 50 MHz Serial RM-10 10 MHz BW, 50 MHz Serial RU-20 10 MHz BW, 17 ns CS Pulse Width RU-10 10 MHz BW, 50 MHz Serial RJ-8 10 MHz BW, 50 MHz Serial CP-40 10 MHz BW, 17 ns CS Pulse Width, 4Quadrant Multiplying Resistors RU-16 10 MHz BW, 50 MHz Serial, 4- Quadrant Multiplying Resistors RU-24 10 MHz BW, 50 MHz Serial, 4- Quadrant Multiplying Resistors RM-10 10 MHz BW, 50 MHz Serial RU-20, CP-20 10 MHz BW, 17 ns CS Pulse Width RU-16 10 MHz BW, 50 MHz Serial RU-24 10 MHz BW, 17 ns CS Pulse Width RJ-8 10 MHz BW, 50 MHz Serial CP-40 10 MHz BW, 17 ns CS Pulse Width, 4Quadrant Multiplying Resistors RU-16 10 MHz BW, 50 MHz Serial, 4- Quadrant Multiplying Resistors RU-24 10 MHz BW, 50 MHz Serial, 4- Quadrant Multiplying Resistors RM-10 10 MHz BW, 50 MHz Serial RU-20, CP-20 10 MHz BW, 17 ns CS Pulse Width RU-24 10 MHz BW, 17 ns CS Pulse Width RU-16 10 MHz BW, 50 MHz Serial RJ-8, RM-8 10 MHz BW, 50 MHz Serial RJ-8, RM-8 10 MHz BW, 50 MHz Serial Future parts, contact factory for availability In development, contact factory for availability OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8 Lead TSOT (UJ-8) 0.122 (3.10) 0.114 (2.90) 8 Lead MSOP (RM-8) 2.90 BSC 8 8 7 6 5 5 1.60 BSC 1 2 3 4 2.80 BSC 0.122 (3.10) 0.114 (2.90) 1 4 0.199 (5.05) 0.187 (4.75) PIN 1 1.00 0.90 0.70 1.95 BSC 0.65 BSC PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 0.120 (3.05) 0.112 (2.84) 0.043 (1.09) 0.037 (0.94) 0.011 (0.28) 0.003 (0.08) 1.10 MAX 0.10 MAX 0.38 0.22 0.20 0.08 8 4 0 O O SEATING PLANE 0.60 0.45 0.30 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) SEATING 0.008 (0.20) PLANE 33 27 O 0.028 (0.71) 0.016 (0.41) -16- REV. PrD |
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